1. Field of the Invention
The present invention relates to an interface circuit for receiving data transferred from a source side, and particularly to a configuration of an interface circuit that receives data transferred in synchronization with a data strobe signal from a memory. More particularly, the present invention relates to a configuration for detecting a transfer mode in a memory interface circuit receiving data from a memory transferring the data in a Double Data Rate (DDR) mode in which the data is transferred in synchronization with rising and falling of a clock signal.
2. Description of the Background Art
For achieving fast data transfer, SDRAMs (Synchronous Dynamic Random Access Memories) that transfer data in synchronization with a clock signal have been widely and generally used. A Double Data Rate mode (DDR mode) in which the data is transferred in synchronization with rising and falling of the clock signal is employed in the SDRAMs used for transferring the data faster.
In the DDR mode, since the data is transferred at a doubled frequency of the clock signal, definite data has a smaller width than that in a Single Data Rate (SDR) mode in which data is transferred in synchronization with either rising or falling of the clock signal. Data transferred between the memory and a controller or a processor (which will be simply referred to as a “controller” hereinbelow). Therefore, when an interconnection line is different from different memories to the controller, a difference occurs in time (flight time) that is required for the transferred data to arrive at a data receiving circuit of the controller.
In the data read operation, the controller issues a data read instruction to a memory, and the data is read from the memory according to the read instruction and is transferred to the controller. Therefore, when the difference is present in length between the interconnection lines from the memories to the controller, a time difference that is greater than at least double the flight time (a round trip time) occurs in time required for transferring the data between the memories and the controller. Therefore, when the controller issues the data read instruction and takes in the transferred data at the same timing, the data cannot be accurately taken in. Therefore, the memory operating in the DDR mode employs a data strobe signal DQS for signaling of timing for transferring the read data. The data strobe signal DQS is a bidirectional strobe signal, and functions as a strobe of data transfer in read and write operations.
In the operation of reading data from a memory, the read data and the data strobe signal DQS are transferred in synchronization with each other from the memory to the controller. In the operation of writing data into a memory, the controller transfers the data strobe signal DQS to the memory together with the write data. In this write operation, an edge of the data strobe signal is present at a center of a window of the write data. When the controller receives the data read from the memory, it internally delays or shifts the phase of the received data strobe signal to a central position of the window of the read data, and takes in the read data according to the internally produced phase-shifted data strobe signal.
The data strobe signal DQS is a ternary signal, and is set to the high-impedance state when data is not transferred. In the data transfer operation, the data strobe signal DQS is set to the L level (logical low level) one clock cycle before the actual data transfer. This data strobe signal DQS is held at the L level before the transfer of the actual data for a period, the period being referred to as a read preamble period (to be simply referred to as a “preamble period” hereinafter). In the operation of reading the data from a memory, the data strobe signal DQS is toggled (changes between the H (logical high) level and L level) in synchronization with the read data subsequently to the preamble period as described above. Since the data transfer is performed in synchronization with the clock signal, the data strobe signal changes with the same frequency as the clock signal. The data transfer is usually performed in a burst mode, and a plurality of data are successively read according to one read instruction. In a cycle in which the last data is transferred, the data strobe signal DQS attains the high-impedance state after it attains the L level. This period of the L level in the cycle of this last data transfer is referred to as a read postamble period (which will be simply referred to as a “postamble period” hereinafter). This postamble period lasts for about half a clock cycle from a leading edge of the last data.
In the data transfer operation, as described above, the data strobe signal DQS changes from the high-impedance state to the preamble state, and changes from the postamble state to the high-impedance state after the data transfer. During transition from the postamble state to the high-impedance state, a glitch noise occurs due to signal reflection.
When the flight time in data transfer from the memory increases, the glitch noise caused after this postamble adversely affects the next data read operation, resulting in a problem that next transfer data is destructed, and the data read from the memory cannot be correctly read-in in the controller.
When the controller is connected to a plurality of data sources, interconnection lengths between the memories and the controller may be different from each other. In this case, the transfer data may be destruct upon being taken in due to the glitch noise. Particularly, in the fast data transfer operation, a window (a period for which effective or valid data is transferred) of the data is short in time width, and a margin for data take-in timing is small, so that the glitch noise is more likely to destruct the data.
A prior art reference 1 (Japanese Patent Laying-Open No. 2005-276396) discloses a construction intending to overcome the problem of the glitch noise of the data strobe signal as described above.
In the configuration disclosed in the prior art reference 1, a delay circuit for delaying a data strobe signal, and a circuit for producing a mask signal based on a delayed data strobe signal produced by the delay circuit are provided, and the delayed data strobe signal and the mask signal are combined to produce a pseudo data strobe signal. The pseudo data strobe signal is toggled during a data establishing period of each time slot of burst data, and is kept at the level attained at the time of end of the toggling for a period from the end of the toggling to the time when all the transfer data are read from a buffer circuit temporarily holding the transfer data. Therefore, the buffer circuit is kept in the data latching state. Thereby, it is intended to mask the glitch noise and to read accurately the data into the memory controller without an influence of the glitch noise.
A prior art reference 2 (Japanese Patent Laying-Open No. 2006-040318) discloses a configuration for suppressing an influence of the glitch noise when the postamble period ends.
In the configuration disclosed in the prior art reference 2, there are provided first and second delay circuits that delay a data strobe signal by different time lengths, respectively, and a buffer circuit that takes in transfer data according to delayed data strobe signals applied from these delay circuits. The first delayed data strobe signal applied from the first delay circuit is used as a clock signal for reading data by the buffer circuit, and the transfer data is taken into a flip-flop in the buffer circuit in an alternate fashion. This flip-flop includes first and second flip-flop circuits that complementarily take in the transfer data according to the first delayed data strobe signal, and a third flip-flop circuit that takes in the data according to the first delayed data strobe signal at the same phase as the second flip-flop circuit. The first and second flip-flop circuits are connected in series, and the first and third flip-flop circuits alternately take in the data. The second and third flip-flop circuits are enabled when the second delayed data strobe signal is active, to take in the data according to the first delayed data strobe signal to transfer the data to internal circuitry of the controller.
The prior art reference 2 utilizes the fact that the second delayed data strobe signal is inactive when the data take-in operation is performed according to the first delayed data strobe signal during the postamble period, to prohibit the take-in of data when the glitch noise occurs in the second and third flip-flop circuits. Thus, it is intended to mask the glitch noise and to prevent destruction of the data due to the glitch noise.
A prior art reference 3 (Japanese Patent Laying-Open No. 2006-013990) discloses a configuration for overcoming a problem of data destruction due to a skew of a data strobe signal. Specifically, the prior art reference 3 relates to the case where the data strobe signal is delayed to produce timing for taking in transfer data in a memory controller, and is configured to reduce the skew of the data strobe signal when a skew is present in data strobe timing with respect to a plurality of data bits, for taking in the data accurately.
In the configuration disclosed in the prior art reference 3, first and second delay elements are arranged in parallel, and are supplied with a clock signal, and a phase comparator compares phases of output signals of the first and second delay elements with each other. According to a result of the comparison, an amount of delay of the second delay element is adjusted. The data read from the memory is taken in according to the output signal of the second delay element. The amount of delay to an input of the phase comparator from the second delay element is made substantially equal to that of delay to a clock input of a flip-flop taking in the transfer data from the second delay element. Thereby, it is intended to reduce jitter in the data strobe signal for performing accurate data transfer.
In the configuration disclosed in the prior art reference 1, the amount of delay for producing the delayed data strobe signal is adjusted using a pattern prepared for calibration. For this, the controller or processor requires a circuit or a configuration for performing the calibration in software or hardware. This results in increase in scale of the software or hardware.
When a plurality of memories are provided, since distances from the respective memories to the controller are different from each other, calibration must be performed for each memory, resulting in a problem that setting of the delay times takes a long time. Operation speeds of the memory and the controller change due to variations in operation condition (temperature and/or power supply voltage), so that a signal transfer time changes, and a round trip time (flight time) changes. Accordingly, the calibration must be performed timely depending on such operation conditions. When the calibration is being performed, the data transfer cannot be performed, so that the process efficiency of the system lowers.
In the configuration disclosed in the prior art reference 2, the delay amount of the second delay circuit producing the mask signal is set by software or a Delay Locked Loop (DLL). The time from production to arrival at the controller of the glitch noise depends on an interconnection length between the memory and the controller. Therefore, the delay amount of the second delay circuit must be set corresponding to each memory.
In the configuration disclosed in the prior art reference 2, the delay amount of the second delay circuit is fixed, e.g., at ⅖ phase of the data strobe signal. When this second delayed data strobe signal is at the H level, the data is taken in using, as the clock signal, a delayed data strobe signal that is delayed by ¼ phase of the data strobe signal and is applied from the first delay circuit. Therefore, in the circuit (flip-flop) producing internal read data of the data thus taken, a period of an enabled state overlaps with an active period of the clock signal only to a small extent, so that it may be impossible to take in the data accurately.
In these prior art references 1 and 2, consideration is given to the phenomenon that the glitch noise caused at the end of the postamble affects the data that has been transferred, but no consideration is given to an influence that is exerted on the take-in of next data by the controller when the glitch noise is transferred with a delay due to the interconnection length. Specifically, in the operation of successively reading the data for different memories with consideration given to burst lengths, a glitch noise of a postamble in the last read cycle may arrive during a preamble period in the current data read operation. In this case, it may be impossible to detect accurately the effective data start timing for reading into data in the current data read operation. In the prior art references 1 and 2, no consideration is given to this problem.
In the configuration disclosed in the prior art reference 3, the timing of the strobe control signal with respect to the flip-flop circuit producing the internal read data is adjusted to accord to the transfer data. In this configuration disclosed in the prior art reference 3, the data transfer within the controller is considered, but no consideration is given to the problem of the glitch noise during the postamble period. It is merely intended to establish synchronization between the transfer data and the data strobe signal.